Accessing system that reduces access times due to transmission delays and I/O access circuitry in a burst mode random access memory
US5410670A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 2, 1993 |
| Grant date | Apr 25, 1995 |
| Priority date | — |
| Expiry date | Jun 2, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C5/025
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A large burst mode memory accessing system includes N discrete sub-memories and three main I/O ports. Data is stored in the sub-memories so that the sub-memories are accessed depending on their proximity to the main I/O ports. Three parallel pipelines provide a data path to/from the main I/O ports and the sub-memories. The first pipeline functions to couple address/control signals to the memories such that adjacent sub-memories are accessed in half cycle intervals. The second pipeline functions to propagate accessed data from the sub-memories to the main I/O ports such that data is outputted from the main output port every successive clock cycle. The third pipeline propagates write data to the memories such that data presented at the input of the third pipeline on successive clock cycles is written into successive sub-memories. Redundancy circuits preserve data integrity without memory access interruption.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.