Method for the etching of a heterostructure of materials of the III-V group
US5411632A · kind A · utility
20Cited by
5References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 5, 1993 |
| Grant date | May 2, 1995 |
| Priority date | — |
| Expiry date | Nov 5, 2013 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/978
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed is a method for the etching of at least two layers of semiconductor materials having different natures, with a view to making a mesa for the self-alignment of the metallizations of a transistor. The heterojunction must comprise a first layer of a material containing As, which is etched by reactive ion etching, and a second layer of a material containing P which is etched chemically. Application to the making of HBT type vertical heterojunction transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.