Silicon-on-insulator CMOS device and a liquid crystal display with controlled base insulator thickness
US5412240A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 14, 1994 |
| Grant date | May 2, 1995 |
| Priority date | — |
| Expiry date | Jul 14, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/201
Abstract
A semiconductor device has an NMOS transistor and a PMOS transistor formed on at least one monocrystal Si region formed in a thin-film Si layer formed on an insulation layer. The thickness T.sub.BOX of the insulation layer on which the NMOS and PMOS transistors are formed, the voltage V.sub.SS of a low-voltage power supply and the voltage V.sub.DD of a high-voltage power supply for the NMOS and PMOS transistors satisfy a relationship expressed by the following equation: EQU T.sub.BOX >(V.sub.DD -V.sub.SS -K.sub.2)/K.sub.1 where K.sub.1 .tbd..epsilon..sub.BOX (Q.sub.BN +Q.sub.BP), K.sub.2 .tbd.2.PHI..sub.FN +2.PHI..sub.FP -1.03, .epsilon..sub.BOX.sup.-1 is the dielectric constant of the base insulation layer, Q.sub.BN and Q.sub.BP are bulk charges when the widths of depletion layers of the NMOS and PMOS transistors are maximized, and .PHI..sub.FN and .PHI..sub.FP are pseudo Fermi potentials of the NMOS and PMOS transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.