PLL clock generator integrated with microprocessor
US5412349A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 31, 1992 |
| Grant date | May 2, 1995 |
| Priority date | — |
| Expiry date | Mar 31, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L2207/06
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A PLL based deskewed clock generator which may be fully integrated on a microprocessor is disclosed. The clock generator has a skew of less than 0.1 ns with peak to peak jitter of 0.3 ns using a 0.8 .mu.m CMOS technology. The PLL comprises a phase frequency detector, charge pump, loop filter and voltage controlled oscillator from which the internal clock is generated. Since the PLL is on the same chip as the microprocessor, it is difficult to isolate the PLL from the noise generated by the microprocessor core logic and output buffers. Without an external filter, noise from the motherboard also influences the PLL. Power supply noise can cause a direct change in the frequency of the voltage controlled oscillator of the PLL. Circuits which overcome the adverse effects which would be created by such noises are also described.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.