Digital signal comparison circuitry
US5412368A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 29, 1993 |
| Grant date | May 2, 1995 |
| Priority date | — |
| Expiry date | Jun 29, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of comparing a first multibit digital signal with a second multibit digital signal wherein to increase speed of obtaining an output signal said method comprises inputting input signals for each of said first and second signals and forming a respective codeword for each input signal, each codeword being at least one bit longer than the respective input signal and formed by the same error correcting code for both signals to provide increased minimum Hamming distance for the respective codewords, comparing respective bit locations of the codewords to form a plurality of match indicating signals for respective bit locations thereby indicating any mismatch by a mismatch at at least two bit locations, supplying said match indicating signals in parallel to gating circuitry arranged to provide an output indicating a match or mismatch between said codewords, said output being provided with a time delay less than that required for a single bit mismatch. The invention also provides digital signal comparison circuitry.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.