Surge arrester circuit and housing therefor
US5412526A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 10, 1993 |
| Grant date | May 2, 1995 |
| Priority date | — |
| Expiry date | Feb 10, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02H9/042
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
The present invention provides a circuit for limiting voltage surges in load centers, panelboards and other electrical distribution devices. The circuit includes at least one high potential terminal adapted for connecting to at least one corresponding service line and a low potential terminal adapted for connecting to a low potential means. The circuit also includes a plurality of varistors connected in parallel to one another between each high potential terminal and the low potential terminal and a plurality of fuses corresponding in number to the plurality of varistors. Each fuse is connected in series to one of the varistors. Each fuse opens the circuit therethrough upon failure of the associated varistor. The circuit further includes monitoring the status condition of the fuses.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.