Variable resolution time slot interchange circuit
US5412657A · kind A · utility
4Cited by
5References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 18, 1993 |
| Grant date | May 2, 1995 |
| Priority date | — |
| Expiry date | Oct 18, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04Q11/08
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
Disclosed is a circuit which allows an n-bit time slot interchanger (TSI) to process m-bit wide information, where m is some fraction of n. A packing circuit receives the information from the TSI in the form of a series of n-bit segments. The circuit will choose m bits from each segment and produce an n-bit output which includes the m-bit segments in a desired order. The n-bit output can then be looped back to the TSI for insertion into an appropriate time slot.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.