Microprogrammed data processor which includes a microsequencer in which a next microaddress output of a microROM is connected to the or-plane of an entry PLA
US5412785A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 26, 1993 |
| Grant date | May 2, 1995 |
| Priority date | — |
| Expiry date | Mar 26, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/265
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processor microsequencer having a non-multiplexed internal address bus is provided. The microsequencer includes a nanoROM, for providing control information to an execution unit, an entry point PLA for decoding a macroinstruction address and providing an initial microinstruction address, and a microROM, for providing the next microinstruction address during instruction sequencing. The entry PLA accesses macroinstructions from an instruction pipeline, and decodes the macroinstructions, thereby providing an initial microinstruction address for the microroutine to perform the macroinstruction. The initial microinstruction address is temporarily stored in a microprogram counter latch (uPC) and provided to the microROM or the nanoROM for decoding. The microROM decodes the initial microinstruction address and provides N output bits which are routed directly into the PLA, and subsequently provided to the uPC. The uPC selectively transfers the next microaddress to the microROM, and the microROM decodes the next microaddress, thereby providing subsequent microaddresses in the microroutine directly to the PLA. Strobe circuitry selectively activates either the microROM and the PLA, and…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.