Microprocessor based systems providing simulated low voltage conditions for testing reset circuits
US5412794A · kind A · utility
5Cited by
11References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 12, 1991 |
| Grant date | May 2, 1995 |
| Priority date | — |
| Expiry date | Nov 12, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A microprocessor system having two microprocessors, each of which has its own reset circuit, and a circuit being provided which detects under-voltage in the system supply voltage, each of said microprocessors having circuitry associated with it for inducing a simulated low voltage condition on the reset circuit of the other microprocessor to test said under-voltage detection circuit and to measure the resulting reset period generated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.