Method of adjusting for clock skew
US5414381A · kind A · utility
31Cited by
17References
3Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 28, 1993 |
| Grant date | May 9, 1995 |
| Priority date | — |
| Expiry date | Jul 28, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus for adjusting signal delay includes an input for receiving a signal to be delay adjusted. A delay circuit is connected to the input means for providing a plurality of selectable signal paths for various delay amounts for producing a delay adjusted signal therefrom. A delay selection circuit is connected to the delay circuit for selecting the signal path so as to select a delay amount and an output provides the delay adjusted signal to a load. Skew compensation is employed on the input and individually on each output to compensate for clock distribution network skew and intracircuit skews, respectively.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.