Four quadrant multiplier circuit and a receiver including such a circuit
US5414383A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 24, 1994 |
| Grant date | May 9, 1995 |
| Priority date | — |
| Expiry date | Feb 24, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03D2200/0033
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A four quadrant multiplier circuit having a high dynamic range and capable of operating at low voltages includes a dual transconductance amplifier circuit (TAC) consisting of NPN transistors (20 to 23 and 64 to 67), coupled to a first input port (36), first and second folded Darlington circuits (57,58), and a resistive element (78). Each Darlington circuit includes first and second NPN transistors (68,70 and 69,71) whose emitter-collector paths are connected in series and a third PNP transistor (72,73) having its emitter-collector path connected between the collector of the first transistor (68,69) and the base electrode of the second transistor (70,71). The emitter-collector junction (76,77) of the first and second transistors (68,70 and 69,71) is connected to the base electrode of the third transistor (72,73). The resistive element (78) is connected between the base electrodes of the third transistors (72,73). A second input port (56) is connected to the base electrodes of the first transistors (68,69). The emitter currents of the dual transconductance amplifier are supplied by way of current mirror circuits (80,81) from the emitter currents of the second transistors (70,71). The…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.