Current source bus terminator with voltage clamping and steady state power reduction
US5414583A · kind A · utility
10Cited by
18References
30Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 14, 1994 |
| Grant date | May 9, 1995 |
| Priority date | — |
| Expiry date | Feb 14, 2014 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A bus terminator, for a computer bus, which is capable of providing maximum allowable current to the bus, voltage clamping of the bus and steady state power reduction when the bus is in the positive steady state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.