Programmable interconnect architecture
US5414638A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 18, 1992 |
| Grant date | May 9, 1995 |
| Priority date | — |
| Expiry date | Dec 18, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K1/18
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A programmable interconnect system includes a two-level hierarchal structure of programmable interconnect chips on a circuit board. The first-level, or "local", interconnect chips are connected to user components. A plurality of second-level, or "global", interconnect chips interconnect the local interconnect chips so that every local chip is connected to every global chip. Such a system allows connecting any pin of any user component to any other pin of any user component by a conductive path passing through at most three interconnect chips. A large number of such paths are provided even in embodiments with a large number of interconnect chips.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.