Asynchronous samples data demodulation system
US5414730A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 21, 1993 |
| Grant date | May 9, 1995 |
| Priority date | — |
| Expiry date | Dec 21, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B1/709
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A novel PN code acquisition and demodulation circuit comprise an analog receiver coupled to an analog to digital converter. The digital output of the converter is passed through an N chip width parallel correlator. The parallel outputs are coherently accumulated to provide N soft decision data values one of which is indicative of the proper replica code for locking onto the data. All of the soft decision data values are stored in a high speed memory in real time. Subsequently non-coherent accumulated soft decision data is employed to detect the proper PN replica code. Logic selection means accesses the soft decision data stored in the high speed memory in non real time and selects the best estimate for the soft decision data and applies the soft decision data to a demodulator in non-real time to recover the hard data encoded in the received PN coded data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.