Adaptive equalizer and method for operation at high symbol rates
US5414732A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | May 17, 1993 |
| Grant date | May 9, 1995 |
| Priority date | — |
| Expiry date | May 17, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03H21/0012
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Adaptive equalizers and processing methods wherein data required to implement an adaptation algorithm is sampled at a rate that is significantly lower than the symbol rate. The adaptation algorithm is processed at this reduced rate, in that updated tap coefficients, sample timing errors and symbol clock error signals are computed at this reduced rate. An advantage of the adaptive equalizer and processing method of the present invention is that the adaptation algorithm may be implemented in equipment that operates at a clock rate that is much less then the symbol rate. In particular, the adaptation algorithm may be computed using software that is resident in inexpensive general purpose digital processor, such as a personal computer, for example. A benefit of the adaptive equalizer and processing method of the present invention is that more sophisticated and more effective adaptation algorithms are practical when compared to adaptive equalizers using algorithms that are constrained to operate at higher symbol rates.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.