Integrated circuit having passive circuit elements
US5416356A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 3, 1993 |
| Grant date | May 16, 1995 |
| Priority date | — |
| Expiry date | Sep 3, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/00
Abstract
An integrated circuit is formed from a first layer of conductive material (30) which is separated from a second layer of conductive material (39) by a layer of dielectric material (36). The first layer of conductive material (30) is patterned to form a first plate (32, 59) of a capacitor (22, 50, 62, 72). An electrical interconnect (33, 63) is formed within the first plate (32, 59), respectively. A via (37) is formed in the layer of dielectric material (36). A second layer of conductive material (39) is patterned to form a second plate (42, 56, 66, 76) of the capacitor (22, 50, 62, 72) and a planar spiral inductor (21, 51, 61, 71). The planar spiral inductor (21, 51, 61, 71) is surrounded by the second plate (42, 56, 66, 76) of the capacitor (22, 50, 62, 72).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.