Differential comparator and analog-to-digital converter comparator bank using the same
US5416484A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Apr 15, 1993 |
| Grant date | May 16, 1995 |
| Priority date | — |
| Expiry date | Apr 15, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/362
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A fully differential comparator includes a differential signal input, a differential reference input, and a differential signal output. Identical first and second gain stages are used in the differential comparator that each have a first single-ended input, a second single-ended input, and a differential output. The first single-ended inputs from the first and second gain stages form the differential signal input of the differential comparator. The second single-ended inputs from the first and second gain stages form the differential reference input of the differential comparator. The differential outputs of the first and second gain stages are cross-coupled to form the differential signal output of the differential comparator. The differential comparator can be used in conjunction with a conventional resistor string found in the front end of a flash ADC, but in a novel manner that prevents undesirable loading effects, as well as other problems associated with prior art single-ended comparators.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.