Single transistor flash EPROM cell and method of operation
US5416738A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | May 27, 1994 |
| Grant date | May 16, 1995 |
| Priority date | — |
| Expiry date | May 27, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3404
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A flash EPROM memory cell array includes a plurality of flash cells arranged as a matrix of rows in columns of said cells. Each cell includes a single transistor. For each row of flash cells in the matrix, a corresponding bit line is connected to the drain region of each memory cell transistor in that row. For each column of flash cells, a corresponding wordline is connected to the control gate of each memory cell transistor in that column. Bias circuitry is provided for applying read bias voltages to the array for reading data from a selected cell in the matrix. The read bias circuitry includes means for applying a first control gate voltage to the wordline connected to the control gate of the selected cell and the second control gate voltage to the deselected wordlines. The first control gate voltage is positive and higher than the highest erased threshold voltage from the erased cell threshold voltage distribution and less than the lowest programmed threshold voltage from the programmed cell threshold distribution such that programmed cells in the selected row are shut off with insignificant drain current conduction. The second control gate voltage is less than the lowest erased…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.