Memory circuit for alternately accessing data within a period of address data
US5416746A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 10, 1992 |
| Grant date | May 16, 1995 |
| Priority date | — |
| Expiry date | Nov 10, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory circuit includes an input selector for receiving input data serially at an interval of a period T and outputting the input data and an address counter for generating first address data sequentially at an interval of a having period 2T and second address data sequentially at an interval having period 2T. The second address data is delayed a period T from the first address data. The memory circuit of the present invention further includes two memory blocks coupled to the input selector and address counter. One memory block stores even numbered input data in response to the first address data and outputs them at the interval of the period 2T. The other memory block stores odd numbered input data in response to the second address data and outputs them at the interval of the period 2T.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.