Built-in self-test flip-flop with asynchronous input
US5416784A · kind A · utility
24Cited by
5References
8Claims
0Family size
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Inventor
Key dates
| Filing date | May 10, 1994 |
| Grant date | May 16, 1995 |
| Priority date | — |
| Expiry date | May 10, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318541
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A BIST cell having a memory element with an asynchronous input in a logic circuit using a built-in self-test mechanism. The BIST cell includes logic to provide a data signal to the memory element during user mode, a reset value to the memory element during reset mode, a scan signal value to the memory element during scan mode, and the sume of the data, reset and scan values during test mode. The BIST cell also prevents the memory element from being reset during test mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.