Method of assembling a monolithic gallium arsenide phased array using integrated gold post interconnects
US5416971A · kind A · utility
4Cited by
8References
1Claims
0Family size
Inventors
Key dates
| Filing date | Jul 28, 1993 |
| Grant date | May 23, 1995 |
| Priority date | — |
| Expiry date | Jul 28, 2013 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49144
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A monolithic gallium arsenide (GaAs) phased array using integrated gold (Au) posts for interconnecting multiple substrate layers. The phased array includes a GaAs substrate having transmit/receive modules fabricated on one side and radiating elements etched on the backside of the same substrate. The conductive gold posts are integrated on the same side with the transmit/receive modules and interconnect the transmit/receive modules with a distribution network which is printed on a second substrate. Gold posts are also used to interconnect DC bias and control lines of the two substrates.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.