Single polysilicon layer E.sup.2 PROM cell

US5418390A · kind A · utility

Assignee

• Lattice Semiconductor Corporation · US

Inventor

• Patrick Wang · Taipei, TW

Key dates

• Filing date: Mar 19, 1993
• Grant date: May 23, 1995
• Expiry date: Mar 19, 2013

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/683

Abstract

An E.sup.2 PROM cell includes a substrate of one conductivity type having source and drain regions of an opposite conductivity type disposed along a surface thereof, with a channel region between the source and drain. An oxide layer is formed over the channel region and includes a relatively thick portion over the channel region, and first and second relatively thin portion over respective portions of the source and drain. Programming of the cell is achieved by electrons passing from the floating gate of the device through the thin oxide portion over the source, while erasing of the cell is undertaken by electrons passing from the drain through the thin oxide portion there over into the floating gate. The cell contains only a single layer of polysilicon, which forms the floating gate.