Logic cell using only two N type transistors for generating each logic function
US5418480A · kind A · utility
18Cited by
5References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 28, 1993 |
| Grant date | May 23, 1995 |
| Priority date | — |
| Expiry date | May 28, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/1737
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A programmable logic cell has two inputs and six outputs, each output being a different logical function of the inputs. Each output is generated by a pair of NMOS transistors, one transistor of each pair having its gate connected to one of the inputs and the other transistor of each pair having its gate connected to the inverse of the same input.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.