Clock signal conditioning circuit
US5418485A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 20, 1993 |
| Grant date | May 23, 1995 |
| Priority date | — |
| Expiry date | Dec 20, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/1565
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A clock signal conditioning circuit (100) for use in a smart card (102) has an input node (112) for receiving an applied clock signal, an output node (126) for producing a conditioned clock signal, a rising/falling edge detector (118) for detecting edges in the received clock signal, a bistable device (122) for forming at the output node a clock signal in response to the edge detector, and a timer (120, 124) for inhibiting switching of the bistable device for a predetermined time (T) following detection by the edge detector of an edge. Such a clock signal conditioning circuit provides a conditioned clock signal which is substantially independent of variations in the duty cycle of the applied clock signal and is substantially immune to glitches in the applied clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.