Fuse state sense circuit
US5418487A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 4, 1992 |
| Grant date | May 23, 1995 |
| Priority date | — |
| Expiry date | Sep 4, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C17/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A fuse state sense circuit includes a fusible link (40) that is disposed between a node (38) and ground. A programming/sense pad (42) is provided to allow voltage to be applied to the node (38) external to the fuse state sense circuit. Current is provided to the node (38) through a current source (30) and a transistor (36). The transistor (36) is controlled by a bias current. An output node (32) is disposed between the current source (30) and the transistor (36). This is connected to the output through an inverter (34). In operation, the voltage on node (38) is raised to a first level to turn off transistor (36) to allow the output to be exercised and to change the state thereof to emulate the fusible link (40) being open. In a second and programming mode, the voltage on the node (38) is raised to a much higher level to allow sufficient current to flow through fusible link (40) to open it. Transistor ( 36) in this mode is rendered non-conductive and isolates the node (38) from the remaining portion of the circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.