Serial data clock recovery circuit using dual oscillator circuit
US5418496A · kind A · utility
11Cited by
3References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 7, 1994 |
| Grant date | May 23, 1995 |
| Priority date | — |
| Expiry date | Feb 7, 2014 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S331/03
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A serial data clock receiver circuit (11) is provided that synchronizes a clock signal to data. The serial data clock receiver circuit (11) comprises a control circuit (21), a dual oscillator circuit (19), and a phase locked loop circuit (22). The control circuit (21) arms the dual oscillator circuit (19) for being enabled during an idle period. The phase locked loop circuit (22) provides a reference voltage for the dual oscillator circuit (19). The dual oscillator circuit (19) is responsive to both the data and control circuit (19) for providing a clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.