Fast communication link bit error rate estimator
US5418789A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 14, 1992 |
| Grant date | May 23, 1995 |
| Priority date | — |
| Expiry date | Oct 14, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/20
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A system and method is provided for estimating the bit error rate of a data signal which has been reconstructed from a received data signal. The system comprises (i) logic for determining timing degradation and amplitude degradation of the received data signal; (ii) an actual bit error rate calculator for calculating the actual bit error rate of the reconstructed data signal; (iii) an instantaneous bit error rate calculator for estimating a bit error rate of the reconstructed signal using the timing degradation and the amplitude degradation; (iv) a first integrator for integrating the estimated bit error rate; (v) a comparator for comparing the integrated estimated bit error rate with the actual bit error rate and outputting an error signal which modifies the estimated bit error rate; and (vi) a second integrator for integrating the estimated bit error rate. The time constant associated with the second integrator is shorter than the time constant associated with the first integrator.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.