Viterbi decoder with path metric comparisons for increased decoding rate and with normalization timing calculation
US5418795A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 3, 1992 |
| Grant date | May 23, 1995 |
| Priority date | — |
| Expiry date | Sep 3, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/0054
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A Viterbi decoding apparatus includes a brand metric calculation circuit for calculating a branch metric for a plurality of time slots at one time by an add-compare-select-state-metric (ACS-SM) calculation circuit for performing add-compare-select (ACS) calculation an add-compare-select-state-metric calculation circuit according to a branch metric for a plurality of time slots obtained by the branch metric calculation circuit and a state metric in the preceding stage at intervals of a plurality of time slots, and a maximum likelihood sequence decision circuit for decoding input data according to the content of the path obtained through the ACS calculation, wherein on the outside of a loop composed of the ACS-SM normalization circuit and a state metric storage circuit, there is provided a normalization command circuit, whereby a decision as to the necessity for normalization, a setting of the timing of normalization, and the like are performed, and, when it is decided that normalization is necessary, the state metric normalized through a bit shifting process in the ACS-SM normalization circuit is selected before at least any one of the state metrics overflows and the selected state …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.