Central processing unit checkpoint retry for store-in and store-through cache systems
US5418916A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 4, 1990 |
| Grant date | May 23, 1995 |
| Priority date | — |
| Expiry date | Oct 4, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0811
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A checkpoint retry system for recovery from an error condition in a multiprocessor type central processing unit which may have a store-in or a store-through cache system. At detection of a checkpoint instruction, the system initiates action to save the content of the program status word, the floating point registers, the access registers and the general purpose registers until the store operations are completed for the checkpointed sequence. For processors which have a store-in cache, modified cache data is saved in a store buffer until the checkpointed instructions are completed and then written to a cache which is accessible to other processors in the system. For processors which utilize store-through cache, the modified data for the checkpointed instructions is also stored in the store buffer prior to storage in the system memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.