Refresh control method and system including request and refresh counters and priority arbitration circuitry
US5418920A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Apr 30, 1992 |
| Grant date | May 23, 1995 |
| Priority date | — |
| Expiry date | Apr 30, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/406
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A refresh control system and method for refreshing DRAM memory in a data processing system, such as a communications system, are disclosed. A timer increments a refresh request counter each time that a desired refresh interval elapses. The contents of the refresh request counter is compared with the contents of a burst refresh counter, and a bus request signal generated responsive to the contents differing from one another, such difference indicating that a refresh operation should be performed. The bus arbitration scheme assigns no higher priority to the refresh priority request than for other bus operations; at such time as bus access is granted to the refresh operation, burst refresh is performed until the contents of the burst refresh counter again match the refresh request counter, at which time the bus is released. An emergency high priority bus request is generated when the difference between the contents of the refresh request counter and the burst counter exceed a given limit, indicating that violation of the refresh specification is imminent.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.