I/O cache controller containing a buffer memory partitioned into lines accessible by corresponding I/O devices and a directory to track the lines
US5418927A · kind A · utility
25Cited by
31References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 23, 1992 |
| Grant date | May 23, 1995 |
| Priority date | — |
| Expiry date | Dec 23, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/084
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A cache for use with input/output devices attached to an input/output bus. Requests for access to system memory by an input/output device pass through the cache. Access authority is checked to determine whether an input/output device is authorized to access that particular page. If it is not, access is denied. Each input/output device has access to a portion of the cache, so that activity by one device will not interfere with activity by another.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.