Bidirectional tri-state data bus buffer control circuit for delaying direction switching at I/O pins of semiconductor integrated circuit
US5418933A · kind A · utility
35Cited by
7References
3Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 3, 1992 |
| Grant date | May 23, 1995 |
| Priority date | — |
| Expiry date | Feb 3, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L5/16
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A data bus control circuit is formed on a single semiconductor integrated circuit that includes input/output terminals for external data exchange and a plurality of functional blocks including a CPU. A bi-directional bus buffer buffers data sent over a data bus between the CPU and the input/output terminals. The signal propagation direction of the bus buffer is determined according to a logic level of a read control signal supplied from the CPU.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.