Double buffer base gate array cell
US5420447A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jan 29, 1993 |
| Grant date | May 30, 1995 |
| Priority date | — |
| Expiry date | Jan 29, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/931
Abstract
A base cell for a CMOS gate array is disclosed, which utilizes cutoff transistor isolation. The disclosed cell implements the cutoff transistor isolation by way of separate outer electrodes for the p-channel and n-channel sides, so that p-type and n-type diffused regions are disposed at the edges of the cell to be shared with adjacent cells. The disclosed cell further includes a pair of inner electrodes which extend over both the n-type and p-type active regions. This construction enables the use of cutoff isolation techniques, but also provides the ability to implement transmission gate style latches via the common complementary gate inner electrodes. Greater efficiency of silicon area, improved utilization, and reduced input loading and active power dissipation result from an integrated circuit incorporate the disclosed cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.