Semiconductor device with conductors on stepped substrate having planar upper surfaces
US5420462A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Apr 12, 1994 |
| Grant date | May 30, 1995 |
| Priority date | — |
| Expiry date | Apr 12, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/31
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An element separating oxide film is formed on a P-type semiconductor substrate by means of a selective oxidation method, and then a gate oxide film is formed on the element separating oxide film by a thermal oxidation method. A gate electrode film made of an N-type polysilicon material is formed so as to extend along a step portion of the element separating oxide film on the semiconductor substrate. The upper surface of the gate electrode film is flattened by means of a surface polishing method. Then, isotropic etching is performed by using a resist pattern as a mask, thereby forming a gate electrode. Since in the method the upper surface of the gate electrode film in the flattened, the semiconductor substrate is prevented from being subject to over-etching when a gage electrode is formed, so that the changes of characteristics of MOS transistors are prevented whose gate insulative films have been becoming thinner as their elements have been finer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.