Memory efficient method and apparatus for sync detection
US5420640A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 3, 1993 |
| Grant date | May 30, 1995 |
| Priority date | — |
| Expiry date | Dec 3, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N21/4435
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A receiver is provided for receiving a digital data stream over a communication path. The digital data is arranged as a sequence of frames, each frame including a plurality of lines of data. The beginning of each frame is indicated by a frame synchronization word; the beginning of each line is indicated by a horizontal synchronization byte. The data is interleaved by an encoder prior to transmission. The decoder contains circuitry for locating the horizontal and frame synchronization data and contains circuitry for deinterleaving the digital data. Both the synchronization locating circuitry and the deinterleaving circuitry require access to a memory, but not at the same time. Therefore, a single memory is used with the synchronization recovery circuitry and deinterleaving circuitry alternately addressing the memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.