Circuitry and method for reducing power consumption within an electronic circuit
US5420808A · kind A · utility
32Cited by
17References
42Claims
0Family size
Assignees
Inventors
Key dates
| Filing date | May 13, 1993 |
| Grant date | May 30, 1995 |
| Priority date | — |
| Expiry date | May 13, 2013 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and circuitry are provided, in which a first operation is performed with first circuitry. A second operation is performed with second circuitry. A first signal is generated in response to the first operation. A second signal is generated in response to the second operation. Power consumption is adjusted within the second circuitry in response to the first and second signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.