Semiconductor integrated circuit device comprising memory area in which structurally different memory cells are included
US5420817A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 16, 1993 |
| Grant date | May 30, 1995 |
| Priority date | — |
| Expiry date | Dec 16, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C17/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The same bit lines are used in common to a fixed data cell array and a memory cell array. The output section of the fixed data cell array is connected to an output circuit, just like the output section of the memory cell array. In response to signal CON supplied from a computer, an array selector examines the states of the arrays and performs switching between the state where one of the arrays can be selected and the state where neither of them can be selected. In the case where an externally-programmable memory, such as an EPROM, is employed, a write control circuit operates with respect only to the memory cell array, and prohibits data from being written in the fixed data cell array. The fixed data cell array is pre-programmed as a nonvolatile memory by programming means different from that used for programming the cells of the memory cell array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.