Coprocessor interface supporting I/O or memory mapped communications
US5420989A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 12, 1991 |
| Grant date | May 30, 1995 |
| Priority date | — |
| Expiry date | Jun 12, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3879
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A coprocessor 18 comprises a bus controller 24 which further comprises a primary bus controller 28 and a secondary bus controller 30 that drive a floating point processor core 26. The primary bus controller 28 comprises a memory mapped bus interface 32 for processing memory mapped format instructions and an I/O bus interface 34 for processing conventional I/O format instructions. The primary bus controller 28 remains essentially transparent for execution of I/O format instructions and translates memory mapped format instructions into sequential bus cycles compatible to an I/O bus interface for processing conventional I/O format instructions, and for execution by the floating point processor core.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.