Memory having concurrent read and writing from different addresses
US5420997A · kind A · utility
Inventors
Key dates
| Filing date | Jan 2, 1992 |
| Grant date | May 30, 1995 |
| Priority date | — |
| Expiry date | Jan 2, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0846
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A random access memory (RAM) complex that can concurrently read and write to different addresses. The memory complex includes two RAMs, each having an address selector, includes a data out multiplexer for selecting outputs from one of the RAM's. A tag array stores an array of tag, one for each address in the RAM's. The tag marks which one of the two RAM's has the valid data for the corresponding read address. During a concurrent read and write cycle, the tag selects the read address for one RAM, selects the write address for the other RAM and a staged copy of the tag controls the multiplexer to select data from the correct RAM for the data out.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.