EEPROM memory device having a sidewall spacer floating gate electrode and process
US5422504A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 2, 1994 |
| Grant date | Jun 6, 1995 |
| Priority date | — |
| Expiry date | May 2, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6892
Abstract
An EEPROM memory array includes a plurality of memory cells having a floating gate electrode (22) formed as a sidewall spacer adjacent to a control gate electrode (20). Source and drain regions (12, 14) reside in a semiconductor substrate (10) and define a segmented channel region (16) therebetween. A select gate electrode (18) overlies a first channel region (24) and separates the floating gate electrode (22) from the source region (12). The control gate electrode (20) overlies a third channel region (28) and separates the floating gate electrode (22) from the drain region (14). The floating gate electrode (22) overlies a second channel region (26) and is separated therefrom by a thin tunnel oxide layer (42). The EEPROM device of the invention can be programmed by either source side injection, or by Fowler-Nordheim tunneling. Additionally, a process is provided for the fabrication of an EEPROM array utilizing adjacent select gate electrodes (18, 18') as a doping mask.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.