Gate array cell with predefined connection patterns

US5422581A · kind A · utility

Assignee

• TEXAS INSTRUMENTS INCORPORATED · US

Inventors

• Shivaling S. Mahant-Shetti · Dallas, US
• Robert J. Landers · Plano, US

Key dates

• Filing date: Aug 17, 1994
• Grant date: Jun 6, 1995
• Expiry date: Aug 17, 2014

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/907

Abstract

A base cell for a CMOS gate array is provided with a first plurality of N-channel transistors 12, 14, 16 with two such N-channel transistors coupled in series. A first plurality of P-channel transistors 50, 52, 54 with two such P-channel transistors coupled in series. These transistors are interconnected at the transistor level to form a partially prewired circuit. Additional pairs of series connected N-channel transistors (18, 20), (22, 24) and pairs of series connected P-channel transistors (56, 58), (60, 62) are also provided and are interconnected at the transistor level to form additional partially prewired circuits. By adding additional levels of wiring 100, 102, the base cell can be finally wired to form a plurality of different logic circuits.