Method and system for screening logic circuits
US5422852A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 2, 1994 |
| Grant date | Jun 6, 1995 |
| Priority date | — |
| Expiry date | Sep 2, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5004
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of testing a circuit having one or more memory cells, such as a random access memory, register or latch, is disclosed herein. A selected pattern (e.g., all "1"s, all "0"s, or alternating "1"s and "0 38 s) is stored (block 10) in each memory cell of the circuit under test. The power to-each of the cells is then lowered (block 12) to a selected voltage level which is below the static holding voltage, but greater than zero volts. The voltage level may have been previously determined. After a selected time period (which may also have been previously determined), the power to each of the cells is restored (block 14) and the logical state present in each cell is compared (block 16) with the initially stored logical state to determine if any of the cells have switched to another logical state. This procedure may be repeated (blocks 18-26) a number of times. Other systems and methods are also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.