Circuit and method for testing direct memory access circuitry
US5423029A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | May 11, 1993 |
| Grant date | Jun 6, 1995 |
| Priority date | — |
| Expiry date | May 11, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/2221
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed are an apparatus and method for testing a direct memory access ("DMA") controller. The apparatus comprises (1) a virtual control device including a virtual control latch, the virtual control device coupled to a request input of the DMA controller and capable of transmitting a signal to the DMA controller representing a request to transfer data and (2) a virtual input/output ("I/O") device including a virtual I/O latch, an acknowledgement output of the DMA controller coupled to the virtual I/O device, the virtual I/O latch capable of storing the data for use by the DMA controller. In its preferred embodiment, the present invention operates within the confines of IBM-compatible personal computer architecture, allowing DMA controller functionality to be tested directly.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.