Method of fabricating NMOS and PMOS FET's in a CMOS process
US5424226A · kind A · utility
10Cited by
11References
2Claims
0Family size
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Key dates
| Filing date | Apr 11, 1994 |
| Grant date | Jun 13, 1995 |
| Priority date | — |
| Expiry date | Apr 11, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
Abstract
A FET which can be formed on a silicon substrate and which can operate in the enhancement mode. The n+ source and drain are centrally located within n-wells which extend under the gate area, and are separated by a distance. By appropriately choosing the distance between n-wells, different threshold voltages can be obtained for several transistors on the same chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.