Method for making contact holes in semiconductor devices
US5424247A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 4, 1992 |
| Grant date | Jun 13, 1995 |
| Priority date | — |
| Expiry date | Aug 4, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In a method for making contact holes in a semiconductor device according to the invention, a first insulating film is deposited on a semiconductor chip, a plurality of contact holes are formed by sequentially performing isotropic etching and anisotropic etching, a second insulating film is deposited after the portions of the first insulating film constituting peripheries of the contact holes are subjected to a reflow process, and residue sidewall insulators are formed for the contact holes by keeping portions of the second insulating film only at sidewall portions of the contact holes when the second Insulating film is etched-back by an anisotropic etching process. The structure thus obtained enables to provide the contact holes whose peripheral edges are gently tapered thereby improving the step coverage of the Interconnect wiring material at the contact hole portions. This enables to avoid a possibility for the interconnect wiring layer to be broken, which may otherwise be caused by a poor step coverage of the interconnect wiring layer. The method enhances the production yield in the fabrication of the device and also enhances the reliability of the product.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.