Bipolar ECL to inverted CMOS level translator
US5424658A · kind A · utility
6Cited by
5References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 10, 1993 |
| Grant date | Jun 13, 1995 |
| Priority date | — |
| Expiry date | Dec 10, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/01812
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A level shifting circuit which can be implemented as part of a bipolar ECL integrated circuit, provides reliable switching and level shifted output suitable for driving a low voltage CMOS integrated circuit. The circuit includes a level shifting circuit which is connected to trigger a high gain positive feedback bootstrap circuit to reliably ensure switching even under poor signal conditions. An output taken from one of the switched pair is allowed to go to V.sub.CC, 0 volts, or is clamped by a clamping circuit to -3.3 volts, representing the two output states suitable for driving inverted rail CMOS circuitry.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.