Non-conductive end layer for integrated stack of IC chips
US5424920A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Apr 25, 1994 |
| Grant date | Jun 13, 1995 |
| Priority date | — |
| Expiry date | Apr 25, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2225/06551
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated stack of layers incorporating a plurality of IC chip layers has an end layer which is formed of dielectric material (or covered with such material). The outer surface of the end layer provides a substantial area for the spaced location of a multiplicity of lead-out terminals, to which exterior circuitry can be readily connected. In the preferred embodiment, each lead-out terminal on the outer surface of the end layer is connected to IC circuitry embedded in the stack by means of conducting material in a hole through the end layer, and a conductor (trace) on the inner surface of the end layer which extends from the hole to the edge of the end layer, where it is connected by a T-connect to metalization on the access plane face of the stack.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.