Mechanism for reducing timing jitter in clock recovery scheme for blind acquisition of full duplex signals
US5425060A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 25, 1993 |
| Grant date | Jun 13, 1995 |
| Priority date | — |
| Expiry date | Jan 25, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/027
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Timing jitter in the clock recovery loop of a `blind` signal acquisition receiver employing a square law detector in a phase lock loop signal flow path is substantially reduced by adaptively adjusting the parameters of the loop's pre-filter, so as to compensate for conjugate antisymmetric components in the spectrum of the monitored signal of interest. The signal timing recovery signal processing mechanism includes a filter parameter adjustment operator which controllably sets the weighting parameters of a baseband prefilter, so that the filtered signal does not possess conjugate antisymmetry about the Nyquist frequency and the spectrum of the filtered signal is essentially conjugate symmetric.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.