Method and apparatus for optimizing high speed performance and hot carrier lifetime in a MOS integrated circuit
US5426375A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 26, 1993 |
| Grant date | Jun 20, 1995 |
| Priority date | — |
| Expiry date | Feb 26, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3011
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
MOS integrated circuit fabrication processes may be optimized for yield rather than for hot carrier lifetime by compensating for oversize MOS channel lengths with increased V.sub.cc power supply voltage, and by compensating for undersized MOS device channel lengths with decreased V.sub.cc. Where channel lengths are greater than necessary, V.sub.cc is increased to increase switching times, while still operating the integrated circuit in a regime ensuring at least a minimum hot carrier lifetime. A test MOS device is fabricated on the integrated circuit substrate and in a test mode the test device substrate current I.sub.bb is measured. The measured I.sub.bb is then correlated with known I.sub.bb data to ascertain whether the channel length and DC hot carrier lifetime are acceptable, both for the test device and all MOS devices in the integrated circuit. The measured I.sub.bb value may be used with a look-up table to manually adjust the V.sub.cc power supply to the integrated circuit to compensate for channel length variation. The measured I.sub.bb value may be translated into a desired compensating value of V.sub.cc, and the integrated circuit so labelled, electrically or by package …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.