High speed processing flip-flop
US5426380A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 30, 1994 |
| Grant date | Jun 20, 1995 |
| Priority date | — |
| Expiry date | Sep 30, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/037
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A high speed processing flip-flop contains a header circuit and a pulse flip-flop circuit. The header circuit is a clock pre-processing circuit that generates clock pulses for operation of the pulse flip-flop circuit, and the pulse flip-flop circuit is a single stage latch. The header circuit contains functional logic including the flip-flop functionality for the high speed processing flip-flop, and any additional processing functions, such as multiplexing. The header circuit also contains a pulse modulator that generates selected clock pulses, based on the functional logic, for the pulse flip-flop circuit. The pulse flip-flop circuit contains storage, a driver circuit, and, for each data input, an input buffer, and a pass gate. The pulse flip-flop circuit couples the data to the driver circuit and storage during an active clock pulse for the corresponding data. Consequently, data input to the pulse flip-flop is not delayed by logic processing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.